Currently, thin wires (bonding wires) having a wire diameter of 20 to 50 μm or so are popularly used as bonding wires for connecting an electrode on a semiconductor element and an external terminal together which is a wiring of a circuit wiring board (a lead frame, a substrate, a tape or the like). A thermal compressive bonding technique with the aid of ultrasound is generally applied to bond bonding wires, and a general-purpose bonding device, and a capillary jig which allows a bonding wire to pass through the interior thereof for connection are used. A leading end of a bonding wire is heated and melted by arc heat inputting, a ball is formed by surface tension, and then the ball is compressively bonded on an electrode of a semiconductor element heated within a range from 150 to 300° C. beforehand. Thereafter, the bonding wire is directly bonded to an external lead by ultrasound compressive bonding.
Recently, technologies related to the structure, material and connection for the semiconductor packaging technologies are rapidly diversified, and for example, in a packaging structure technology, in addition to currently-used QFP (Quad Flat Packaging) using a lead frame, new configurations, such as BGA (Ball Grid Array) using a substrate, a polyimide tape or the like and CSP (Chip Scale Packaging) are practically used, and a bonding wire which has improved loop characteristic, bonding property, mass productivity, usability and the like becomes requisite.
Introduction of a fine pitch technique that a space between adjacent bonding wires becomes narrow has progressed. Thinning, improvement of strength, loop controllability, and bonding property become requisite for bonding wires in accordance with the introduction of the fine pitch technique. A loop shape becomes complex together with the density growth of the semiconductor packaging technologies. A loop height and a wire length (span) of a bonding wire are barometers for classification of the loop shape. In most-recent semiconductor devices, contradictory loop shapes, such as a high loop and a low loop, and, a short span and a long span, are mixed within the interior of a single package. In order to realize such contradictory loop shapes with a bonding wire of one kind, a strict designing of a material of a bonding wire is essential.
So far, 4N-group gold having a high purity (purity >99.99% by weight) is used as a material of a bonding wire. In order to improve strength and a bonding property, a tiny amount of alloy elements are prepared. Recently, a gold alloy wire with a purity of 2N (purity >99%) that an additive element concentration is increased to less than or equal to 1% becomes into practical use in order to improve the reliability of a bonded part. The strength can be improved and the reliability can be controlled by adjusting the kind and the concentration of an alloy element added to gold. Conversely, alloying may cause deterioration of a bonding property and increment of an electrical resistance, so that it is difficult to comprehensively satisfy various characteristics requisite for the bonding wires.
Moreover, because gold is expensive, other kinds of metals which have a low material cost are desired, and bonding wires which have a low material cost, have a good electrical conductivity and are made of copper are created. According to the copper bonding wires, however, a bonding strength is reduced due to oxidization of a wire surface, and a wire surface is likely to be corroded when encapsulated in a resin. These are the reasons that practical usage of the copper bonding wires is not accelerated.
All bonding wires in practical use so far have a monolayer structure. Even if materials, such as gold and copper, are changed, alloy elements are uniformly contained in a bonding wire, and a wire monolayer structure is employed as viewed from a cross section of a bonding wire. A thin native oxide film, an organic film for protecting a surface and the like may be formed on a wire surface of a bonding wire in some cases, these are limited in an extremely-thin area (up to several atomic layer level) in an outermost surface.
In order to meet various needs requisite for the bonding wires, a bonding wire with a multilayer structure in which a wire surface is coated with another metal is proposed.
As a technique of suppressing any oxidization of a surface of a copper bonding wire, patent literature 1 discloses a bonding wire in which copper is covered with a noble metal or a corrosion-resistant metal, such as gold, silver, platinum, palladium, nickel, cobalt, chrome, titanium, and the like. Moreover, from the standpoint of a ball formability and suppression of deterioration of a plating solution, patent literature 2 discloses a bonding wire so structured as to have a core member mainly composed of copper, a dissimilar metal layer formed on the core member and made of a metal other than copper, and a coating layer formed on the dissimilar metal layer and made of an oxidization-resistant metal having a higher melting point than copper. Patent literature 3 discloses a bonding wire comprising a core member mainly composed of copper, and an outer skin layer which contains a metal, having either one of or both of a constituent and a texture different from the core member, and copper, and which is a thin film having a thickness of 0.001 to 0.02 μm.
Various gold bonding wires with a multilayer structure have been proposed. For example, patent literature 4 discloses a bonding wire comprising a core wire formed of highly-pure Au or Au alloy, and a coating material coating an outer surface of the core wire and formed of a highly-pure Pd or Pd alloy. Patent literature 5 discloses a bonding wire comprising a core wire formed of highly-pure Au or Au alloy, and a coating material coating an outer surface of the core wire and formed of highly-pure Pt or Pt alloy. Patent literature 6 discloses a bonding wire comprising a core wire formed of highly-pure Au or Au alloy, and a coating material coating an outer surface of the core wire and formed of highly-pure Ag or Ag alloy.
It is desirable to cope with the most advanced fine pitch technique and high-density packaging technique like three-dimensional wiring by satisfying comprehensive characteristics such that loop control is stable in a bonding process, a bonding property is improved, deformation of a bonding wire at the time of resin encapsulation is suppressed, and a long-term reliability of a bonded part is accomplished as wire characteristics of a bonding wire of mass-production.
Regarding ball bonding, it is important to form a ball with a good sphericity at the time of ball formation, and to obtain a sufficient bonding strength between the ball and an electrode. Moreover, in order to cope with lowering of a bonding temperature and thinning of a bonding wire, a bonding strength, a tensile strength and the like are requisite at a part where a bonding wire is subjected to wedge bonding to a wiring on a circuit wiring board.
A surface nature of a wire affects a use performance, and for example, merely creation of a flaw and that of scraping make mass-production difficult. Adjoining bonding wires may be electrically short-circuited due to scraping, and a flaw makes the quality and reliability of a bonding wire, such as a manufacturing yield of a bonding wire and wire deformation at the time of resin encapsulation, deteriorated. Moreover, practical use cannot be accomplished if strict requisitions such that a failure occurrence rate of a semiconductor manufacturing process is managed in a ppm order are not satisfied by further pursuing a stability of loop-shape control and by further improving a bonding property at a low temperature.
Such bonding wires with a multilayer structure for semiconductors have large anticipation for practical use, but have not become in practical use. Reforming of a surface, a high added value, and the like by the multilayer structure is anticipated, but in contrast, it is necessary to comprehensively satisfy a productivity of a bonding wire, a quality thereof, a yield in a bonding process, performance stability, and a long-term reliability at the time of semiconductor usage.    Patent Literature 1: JPS62-97360A    Patent Literature 2: JP2004-64033A    Patent Literature 3: JP2007-12776A    Patent Literature 4: JPH04-79236A    Patent Literature 5: JPH04-79240A    Patent Literature 6: JPH04-79242A